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P4C1256 HIGH SPEED 32K x 8 STATIC CMOS RAM
FEATURES
High Speed (Equal Access and Cycle Times) -- 12/15/20/25/35 ns (Commercial) -- 15/20/25/35/45 ns (Industrial) -- 20/25/35/45/55/70 ns (Military) Low Power Single 5V10% Power Supply Easy Memory Expansion Using CE and OE Inputs Common Data I/O Three-State Outputs Fully TTL Compatible Inputs and Outputs Advanced CMOS Technology Fast tOE Automatic Power Down Packages --28-Pin 300 mil DIP, SOJ, TSOP --28-Pin 300 mil Ceramic DIP --28-Pin 600 mil Ceramic DIP --28-Pin CERPACK --28-Pin SOP --28-Pin LCC (350 mil x 550 mil) --32-Pin LCC (450 mil x 550 mil)
DESCRIPTION
The P4C1256 is a 262,144-bit high-speed CMOS static RAM organized as 32Kx8. The CMOS memory requires no clocks or refreshing, and has equal access and cycle times. Inputs are fully TTL-compatible. The RAM operates from a single 5V10% tolerance power supply. Access times as fast as 12 nanoseconds permit greatly enhanced system operating speeds. CMOS is utilized to reduce power consumption to a low level. The P4C1256 is a member of a family of PACE RAMTM products offering fast access times.
The P4C1256 device provides asynchronous operation with matching access and cycle times. Memory locations are specified on address pins A0 to A14. Reading is accomplished by device selection (CE and output enabling (OE) while write enable (WE) remains HIGH. By presenting the address under these conditions, the data in the addressed memory location is presented on the data input/output pins. The input/output pins stay in the HIGH Z state when either CE or OE is HIGH or WE is LOW. Package options for the P4C1256 include 28-pin 300 mil DIP, SOJ and TSOP packages. For military temperature range, Ceramic DIP and LCC packages are available.
FUNCTIONAL BLOCK DIAGRAM
PIN CONFIGURATIONS
DIP (P5, C5, C5-1, D5-2), SOJ (J5), SOP (S11-1, S11-3) CERPACK (F4) SIMILAR
1519B See end of datasheet for LCC and TSOP pin configurations.
Document # SRAM119 REV G 1 Revised June 2007
P4C1256
MAXIMUM RATINGS(1)
Symbol V CC Parameter Power Supply Pin with Respect to GND Terminal Voltage with Respect to GND (up to 7.0V) Operating Temperature Value -0.5 to +7 -0.5 to VCC +0.5 -55 to +125 Unit V Symbol TBIAS TSTG V C PT IOUT Parameter Temperature Under Bias Storage Temperature Power Dissipation DC Output Current Value -55 to +125 -65 to +150 1.0 50 Unit C C W mA
V TERM TA
RECOMMENDED OPERATING TEMPERATURE AND SUPPLY VOLTAGE
Grade(2) Military Ambient Temperature GND 0V 0V 0V VCC 5.0V 10% 5.0V 10% 5.0V 10%
CAPACITANCES(4)
VCC = 5.0V, TA = 25C, f = 1.0MHz Symbol CIN COUT Parameter Input Capacitance Conditions Typ. Unit VIN = 0V 8 10 pF pF
-55C to +125C -40C to +85C Industrial Commercial 0C to +70C
Output Capacitance VOUT = 0V
DC ELECTRICAL CHARACTERISTICS
Over recommended operating temperature and supply voltage(2) Symbol VIH VIL V HC VLC VOL VOH Parameter Input High Voltage Input Low Voltage CMOS Input High Voltage CMOS Input Low Voltage Output Low Voltage (TTL Load) Output High Voltage (TTL Load) Input Leakage Current IOL = +8 mA, VCC = Min. IOH = -4 mA, VCC = Min. VCC = Max. VIN = GND to VCC VCC = Max., ILO Output Leakage Current CE = VIH, VOUT = GND to VCC CE VIH ISB Mil. ___ ___ 45 30 ___ ___ 30 n/a mA Mil. Ind./Com'l. Mil. Ind./Com'l. 2.4 -10 -5 -10 -5 +10 +5 +10 +5 Test Conditions P4C1256 Min Max VCC +0.5 2.2 P4C1256L Unit Min Max VCC +0.5 V 2.2 V V V V V +5 n/a +5 n/a A A
0.8 0.8 -0.5(3) -0.5(3) VCC -0.2 VCC +0.5 VCC -0.2 VCC +0.5 -0.5
(3)
0.2 0.4
-0.5
(3)
0.2 0.4
2.4 -5 n/a -5 n/a
ILI
Standby Power Supply VCC= Max, Ind./Com'l. Current (TTL Input Levels) f = Max., Outputs Open
CE VHC ISB1 Standby Power Supply Current (CMOS Input Levels) VCC= Max, f = 0, Outputs Open VIN VLC or VIN VHC
Mil. Ind./Com'l.
___ ___
20 10
___ ___
10 n/a
mA
N/A = Not Applicable
Document # SRAM119 REV G
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P4C1256
DATA RETENTION CHARACTERISTICS (P4C1256L Military Temperature Only)
Symbol V DR ICCDR t CDR tR
*TA = +25C tRC = Read Cycle Time
Parameter VCC for Data Retention Data Retention Current Chip Deselect to Data Retention Time Operation Recovery Time
Test Conditons
Min 2.0
Typ.* VCC = 2.0V 3.0V
Max VCC = 2.0V 3.0V
Unit V
CE VCC -0.2V, VIN VCC -0.2V or VIN 0.2V 0 tRC
10
15
100
200
A ns ns
This parameter is guaranteed but not tested.
DATA RETENTION WAVEFORM
POWER DISSIPATION CHARACTERISTICS VS. SPEED
Symbol Parameter Temperature Range Commercial Military -12 170 N/A N/A -15 160 170 N/A -20 155 165 170 -25 150 160 165 -35 145 155 160 -45 N/A 150 155 -55 N/A N/A 150 -70 N/A N/A 150 Unit mA mA mA
ICC
Dynamic Operating Current* Industrial
*VCC = 5.5V. Tested with outputs open. f = Max. Switching inputs are 0V and 3V. CE = VIL, OE = VIH.
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P4C1256
AC ELECTRICAL CHARACTERISTICS--READ CYCLE
(VCC = 5V 10%, All Temperature Ranges)(2)
Sym. t RC tAA t AC t OH tLZ t HZ tOE
Parameter Read Cycle Time Address Access Time Chip Enable Access Time Output Hold from Address Change Chip Enable to Output in Low Z Chip Disable to Output in High Z Output Enable Low to Data Valid Output Enable Low to Low Z Output Enable High to High Z Chip Enable to Power Up Time Chip Disable to Power Down Time 0 0 2 2
-12 12 12 12 2 2 5 5
-15 15 15 15 2 2 8 7 20
-20 25 20 20 3 3 9 9
-25 35 25 25 3 3 11 10
-35 45 35 35 3 3 15 15
-45 55 45 45 3 3 20 20
-55 70 55 55 3 3 25 25
-70
Unit ns
Min Max Min Max Min Max Min Max Min Max Min Max Min Max Min Max
70 70
ns ns ns ns
30 30
ns ns
tOLZ t OHZ t PU t PD
0 5 0 12 15 7
0 9 0 20
0 11 0 20
0 15 0 20
0 20 0 25
0 25 0 30
0 30 0 35
ns ns ns ns
Document # SRAM119 REV G
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P4C1256
TIMING WAVEFORM OF READ CYCLE NO. 1 (OE CONTROLLED)(5) OE
TIMING WAVEFORM OF READ CYCLE NO. 2 (ADDRESS CONTROLLED)(5,6)
TIMING WAVEFORM OF READ CYCLE NO. 3 (CE CONTROLLED)(5,7) CE
Notes: 1. Stresses greater than those listed under MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to MAXIMUM rating conditions for extended periods may affect reliability. 2. Extended temperature operation guaranteed with 400 linear feet per minute of air flow. 3. Transient inputs with VIL and IIL not more negative than -3.0V and -100mA, respectively, are permissible for pulse widths up to 20 ns.
4. This parameter is sampled and not 100% tested. 5. WE is HIGH for READ cycle. 6. CE is LOW and OE is LOW for READ cycle. 7. ADDRESS must be valid prior to, or coincident with CE transition LOW. 8. Transition is measured 200 mV from steady state voltage prior to change, with loading as specified in Figure 1. This parameter is sampled and not 100% tested. 9. Read Cycle Time is measured from the last valid address to the first transitioning address.
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P4C1256
AC CHARACTERISTICS--WRITE CYCLE
(VCC = 5V 10%, All Temperature Ranges)(2)
Sym. tWC tCW
Parameter
-12
-15 15 10 20
-20 25
-25 35 22
-35 45
-45 55
-55 70
-70
Min Max Min Max Min Max Min Max Min Max Min Max Min Max Min Max
Unit ns ns
Write Cycle Time 12 Chip Enable Time to End of Write Address Valid to End of Write Address Set-up Time Write Pulse Width Address Hold Time Data Valid to End of Write Date Hold Time Write Enable to Output in High Z Output Active from End of Write 3 9
15
18
30
35
40
tAW tAS tWP tAH tDW t DH tWZ tOW
9 0 9 0 8 0 7
10 0 11 0 9 0 8 3
15 0 15 0 11 0 10 3
20 0 18 0 13 0 11 3
25 0 22 0 15 0 15 5
35 0 25 0 20 0 18 5
40 0 30 0 25 0 25 0
45 0 35 0 30 0 30 0
ns ns ns ns ns ns ns ns
WE TIMING WAVEFORM OF WRITE CYCLE NO. 1 (WE CONTROLLED)(10,11)
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P4C1256
TIMING WAVEFORM OF WRITE CYCLE NO. 2 (CE CONTROLLED)(10) CE
Notes: 10. CE and WE must be LOW for WRITE cycle. 11. OE is LOW for this WRITE cycle to show tWZ and tOW. 12. If CE goes HIGH simultaneously with WE HIGH, the output remains
in a high impedance state 13. Write Cycle Time is measured from the last valid address to the first transitioning address.
Document # SRAM119 REV G
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P4C1256
AC TEST CONDITIONS
Input Pulse Levels Input Rise and Fall Times Input Timing Reference Level Output Timing Reference Level Output Load GND to 3.0V 3ns 1.5V 1.5V See Figures 1 and 2
TRUTH TABLE
Mode Standby Standby DOUT Disabled Read Write CE O E W E H X L L L X X H L X X X H H L I/O High Z High Z High Z DOUT High Z Power Standby Standby Active Active Active
Figure 1. Output Load
* including scope and test fixture. Note: Because of the ultra-high speed of the P4C1256, care must be taken when testing this device; an inadequate setup can cause a normal functioning part to be rejected as faulty. Long high-inductance leads that cause supply bounce must be avoided by bringing the VCC and ground planes directly up to the contactor fingers. A 0.01 F high frequency capacitor is also required between VCC and ground. To avoid signal reflections, proper termination
Figure 2. Thevenin Equivalent
must be used; for example, a 50 test environment should be terminated into a 50 load with 1.73V (Thevenin Voltage) at the comparator input, and a 116 resistor must be used in series with DOUT to match 166 (Thevenin Resistance).
Document # SRAM119 REV G
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P4C1256
ORDERING INFORMATION
SELECTION GUIDE
The P4C1256 is available in the following temperature, speed and package options. The P4C1256L is available only over the military temperature range. **
Temperature Range Commercial Speed Package Plastic DIP Plastic SOJ Plastic TSOP Plastic SOP (S11-1) Industrial Plastic SOP (S11-3) Plastic DIP Plastic SOJ Plastic TSOP Plastic SOP (S11-1) Plastic SOP (S11-3) 12 -12PC -12JC -12TC -12SC -12SSC N/A N/A N/A N/A N/A 15 -15PC -15JC -15TC -15SC -15SSC -15PI -15JI -15TI -15SI -15SSI 20 -20PC -20JC -20TC -20SC -20SSC -20PI -20JI -20TI -20SI -20SSI 25 -25PC -25JC -25TC -25SC -25SSC -25PI -25JI -25TI -25SI -25SSI 35 -35PC -35JC -35TC -35SC -35SSC -35PI -35JI -35TI -35SI -35SSI 45 N/A N/A N/A N/A N/A -45PI -45JI -45TI -45SI -45SSI 55 N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A 70 N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A
* Military temperature range with MIL-STD-883, Class B processing. ** For RoHS compliant plastic products, the suffix "LF" (Lead Free) should be added to the part number. N/A = Not Available
Document # SRAM119 REV G
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P4C1256
SELECTION GUIDE (CONTINUED)
Temperature Range Military Temperature Package Side Brazed DIP (300 mil) Side Brazed DIP (600 mil) Ceramic DIP CERPACK LCC (28-Pin) LCC (32-Pin) Military Processed* Side Brazed DIP (300 mil) Side Brazed DIP (600 mil) Ceramic DIP CERPACK LCC (28-Pin) LCC (32-Pin) Speed 12 N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A 15 N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A 20 -20CM -20CWM -20DM -20FM -20L28M -20L32M -20CMB -20CWMB -20DMB -20FMB -20L28MB -20L32MB 25 -25CM -25CWM -25DM -25FM -25L28M -25L32M -25CMB -25CWMB -25DMB -25FMB -25L28MB -25L32MB 35 -35CM -35CWM -35DM -35FM -35L28M -35L32M -35CMB -35CWMB -35DMB -35FMB -35L28MB -35L32MB 45 -45CM -45CWM -45DM -45FM -45L28M -45L32M -45CMB -45CWMB -45DMB -45FMB -45L28MB -45L32MB 55 -55CM -55CWM -55DM -55FM -55L28M -55L32M -55CMB -55CWMB -55DMB -55FMB -55L28MB -55L32MB 70 -70CM -70CWM -70DM -70FM -70L28M -70L32M -70CMB -70CWMB -70DMB -70FMB -70L28MB -70L32MB
LCC PIN CONFIGURATIONS
28 LCC (L5)
32 LCC (L6)
TSOP (T1)
Document # SRAM119 REV G
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P4C1256
Pkg # # Pins Symbol A b b2 C D E eA e L Q S1 S2
C5
28 (300 mil) Min Max 0.225 0.014 0.026 0.045 0.065 0.008 0.018 1.485 0.240 0.310 0.300 BSC 0.100 BSC 0.125 0.200 0.015 0.070 0.005 0.005 -
SIDE BRAZED CERAMIC DUAL IN-LINE PACKAGE (300 Mils)
Pkg # # Pins Symbol A b b2 C D E eA e L Q S1 S2
C5-1
28 (600 mil) Min Max 0.232 0.014 0.026 0.045 0.065 0.008 0.018 1.490 0.500 0.610 0.600 BSC 0.100 BSC 0.125 0.200 0.015 0.060 0.005 0.005 -
SIDE BRAZED CERAMIC DUAL IN-LINE PACKAGE (600 Mils)
Document # SRAM119 REV G
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P4C1256
Pkg # # Pins Symbol A b b2 C D E eA e L Q S1
D5-2
28 (300 mil) Min Max 0.225 0.014 0.026 0.045 0.065 0.008 0.018 1.485 0.240 0.310 0.300 BSC 0.100 BSC 0.125 0.200 0.015 0.060 0.005 0 15
CERDIP DUAL IN-LINE PACKAGE
Pkg # # Pins Symbol A b c D E e k L Q S S1
F4
28 Min Max 0.060 0.090 0.015 0.022 0.004 0.009 0.730 0.330 0.380 0.050 BSC 0.005 0.018 0.250 0.370 0.026 0.045 0.085 0.005 -
CERPACK CERAMIC FLAT PACKAGE
Document # SRAM119 REV G
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P4C1256
Pkg # # Pins Symbol A A1 b C D e E E1 E2 Q
J5
28 (300 mil) Min Max 0.120 0.148 0.078 0.014 0.020 0.007 0.011 0.700 0.730 0.050 BSC 0.335 BSC 0.292 0.300 0.267 BSC 0.025 -
SOJ SMALL OUTLINE IC PACKAGE
Pkg # # Pins Symbol A A1 B1 D D1 D2 D3 E E1 E2 E3 e h j L L1 L2 ND NE
L5
28 Min Max 0.060 0.075 0.050 0.065 0.022 0.028 0.342 0.358 0.200 BSC 0.100 BSC 0.358 0.540 0.560 0.400 BSC 0.200 BSC 0.558 0.050 BSC 0.040 REF 0.020 REF 0.045 0.055 0.045 0.055 0.075 0.095 5 9
RECTANGULAR LEADLESS CHIP CARRIER (28 Pins)
Document # SRAM119 REV G
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P4C1256
Pkg # # Pins Symbol A A1 B1 D D1 D2 D3 E E1 E2 E3 e h j L L1 L2 ND NE
L6
32 Min Max 0.060 0.075 0.050 0.065 0.022 0.028 0.442 0.458 0.300 BSC 0.150 BSC 0.458 0.540 0.560 0.400 BSC 0.200 BSC 0.558 0.050 BSC 0.040 REF 0.020 REF 0.045 0.055 0.045 0.055 0.075 0.095 7 9
RECTANGULAR LEADLESS CHIP CARRIER (32 Pins)
Pkg # # Pins Symbol A A1 b b2 C D E1 E e eB L
P5
28 (300 mil) Min Max 0.210 0.014 0.023 0.045 0.070 0.008 0.014 1.345 1.400 0.270 0.300 0.300 0.380 0.100 BSC 0.430 0.115 0.150 0 15
PLASTIC DUAL IN-LINE PACKAGE
Document # SRAM119 REV G
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P4C1256
Pkg # # Pins Symbol A A2 b D E e HD
T1
28 Min Max 0.039 0.047 0.036 0.040 0.007 0.011 0.461 0.469 0.311 0.319 0.022 BSC 0.520 0.535
TSOP THIN SMALL OUTLINE PACKAGE (8 x 13.4 mm)
Pkg # # Pins Symbol A A1 b2 C D e E H h L
S11-1
28 (300 Mil) Min Max 0.093 0.104 0.004 0.012 0.013 0.020 0.009 0.012 0.696 0.712 0.050 BSC 0.291 0.299 0.394 0.419 0.010 0.029 0.016 0.050 0 8
SOIC/SOP SMALL OUTLINE IC PACKAGE
Document # SRAM119 REV G
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P4C1256
Pkg # # Pins Symbol A A1 B C D e E H h L
S11-3
28 (300 Mil) Min Max 0.094 0.110 0.002 0.014 0.014 0.020 0.008 0.012 0.702 0.710 0.050 BSC 0.291 0.300 0.463 0.477 0.010 0.029 0.020 0.042 0 8
SOIC/SOP SMALL OUTLINE IC PACKAGE
Document # SRAM119 REV G
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P4C1256
REVISIONS
DOCUMENT NUMBER: DOCUMENT TITLE: REV. OR A B C D E F G ISSUE DATE 1997 Oct-05 Oct-05 Apr-06 May-06 Jun-06 Aug-06 Jun-07 SRAM119
HIGH SPEED 32K x 8 STATIC CMOS RAM
ORIG. OF CHANGE RKK JDB JDB JDB JDB JDB JDB JDB
DESCRIPTION OF CHANGE New Data Sheet Change logo to Pyramid Added SOP Package Added Lead-Free ordering information. Added PDIP to Ordering Information diagram Added Ceramic DIP package Updated SOJ package information Corrected SOP package information
Document # SRAM119 REV G
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